1101

Intel 1101	Intel 1101	Intel C 1101 A	Intel C 1101 A1	Intel P 1101

Intermediate manufacturing stages:   

Intel 1101 without marking	Intel 1101 without marking and cover

AMD C 1101 A	AMD P1101 A	AMD C 1101 A1	Microsystems International Limited ML 1101 A	Microsystems International Limited MF 1101 AR	National Semiconductor MM 1101 AD

Concept: Ted Hoff
Design: Joel Karp
Projectmanagement: Les Vadasz
First RAM; developed to replace the core memory; among the competing MOS-, bipolar- and multiple-chip-systems in the end only the MOS process on silicon-gate-basis was successful; the first 1101 devices were manufactured in a former Union Carbide factory in Mountain View; later (in the end of 1971) the production moved to Santa Clara

1103

mask of chip die
(1 MB)

Concept: Ted Hoff
Design: John Reed
This first DRAM is also the first of the chips that would enable the explosive growth of PC's; 1970 MIL became the official second source supplier for Intels 1103;  MIL deviated from Intels specification to increase the yield by means of reducing the chip area and enlarging the wafers but the yield decreased to almost zero. Intel stepped into the breach and satisfied nearly the whole market need for 1103; in the end of 1971 Intel delivered the 1103 to 14 of the 18 leading computer manufacturers.
Since the production costs of the 1103 were much lower than the costs of a core memory or a 1101 the 1103 could establish within the market rapidly, became the world's best selling memorychip and was finally responsible for the obsolescence of magnetic core memory.

The 1103 is a 1K bit PMOS Dynamic Random Access Memory (DRAM) chip; refreshing of all 1024 bits is accomplished in 32 read cycles and is required every two milliseconds.

1301

2048-bit mask programmable MOS ROM; programmed by a metal mask; ideal for large volume and lower cost production runs of systems initially using the 1601 / 1701 or the static only 1602 / 1702; the dynamic mode of the 1301 refers to the decoding circuitry and not to the memory cell

1302

2048-bit mask programmable PMOS ROM

1601

Fabricated with silicon gate technology; 256 word by 8 bit electrically programmable ROM suited for uses where fast turnaround and pattern experimentation were important such as in prototype or in one of a kind systems; factory reprogrammable which allowed Intel to perform a complete programming and functional test on each bit position before delivery.
inputs and outputs DDT and TTL compatible; static and dynamic operation; the 1601 uses an identical chip related to 1602, 1701 and 1702.

1602

Fabricated with silicon gate technology; 256 word by 8 bit electrically programmable ROM suited for uses where fast turnaround and pattern experimentation were important such as in prototype or in one of a kind systems; field programmable;  factory reprogrammable; operable in static mode only;
inputs and outputs DDT and TTL compatible; the 1602 uses an identical chip related to 1601, 1701 and 1702.

1701

First EPROM to use a floating polysilicon gate as a storage element; 2-Kb device programmable with special hardware and erasable with ultraviolet light. Introduced six months earlier than the 1201, the 1701 was a solution looking for a problem. However, it made possible the development of a board that you could use to develop, run, and debug software for the MCS-4.

1702

Design: Dov Frohman, Joe Friedrich
In the beginning of 1970 the market needs for this chip was enormous but the yield of the first 1702 production was very poor. On each functional chip there were hundreds of unuseable chips. After modification of chip architecture from parallel in serial design and including the Walkout (put the chips under high negative voltage) into the manufacturing process the production yield suddenly increased to 60 chips per wafer. After modification of this production process the chip was marked 1702 A.

256 word by 8-bit electrically programmable ROM; ideally suited for uses where fast turn-around and pattern experimantation are important; transparent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern; a new pattern can then be written into the device; fabricated with silicon gate technology; 

2102

High speed 1024 word by one bit static random access element using N-channel MOS devices integrated on a monolithic array; directly TTL compatible in all respects: input, output and a single +5 V volt supply; standby power mode; 2102A-2 access in 250 ns

2600

2048-bit; static operation; TTL compatible; programming the memory content and output buffer configuration is accomplished by changing a single mask during device fabrication; inputs are available for enabling the chip and for selecting between a memory organization of 512 words of four bits or 256 words of eight bits; 

3101

mask of chip die;
(774 kB)

Very first product of Intel; bipolar device; during the development of computer technology the MOS and bipolar techniques were direct competitors;

Dick Bohn: Responsible project manager for bipolar devices
H.T.Chua: Responsible project manager for 3101

Honeywell initiated the 3101 project by means of a part payment of $ 10.000. They intended to develop a computer series including a 64-bit storage sufficient for English word lenghts of 8 characters.
In comparison with the MOS technique the bipolar technique retreated into the background more and more. In the end the bipolar devices eked out its existance as a minor product for fast applications.

16 x 4 bit High Speed RAM; fast access time - 35 nsec. max. over 0-75°C temperature range; simple memory expansion through chip select input - 17 nsec. max. over 0-75°C temperature range; high speed fully decoded 64 bit random access memory, organized 16 words by 4 bits; the use of Shottky barrier diode clamped transistors to obtain fast switching speed results in higher performance than equivalent devices with gold diffusion processes; packaged in either hermetically sealed 16 pin ceramic packages, or in low cost silicone packages, and their performance is specified over a temperature range from 0° to 75°C;
the first 1101 chips were manufactured in a former plant of Union Carbide in Mountain View; later, in the end of 1971, in Santa Clara

3301

1024-bit mask programmable Schottky Bipolar Decoder; the 3301 A was a higher speed version of the 3301 and was a direct pin-for-pin replacement of the 3301; its performance was specified over the complete ambient temperature range of 0 °C to 75 °C and a Vcc supply voltage range of 5 V ± 5 %; programmed at the final step of processing which allowed fast turnaround; the 3301 A was mask programmed to customized patterns; it was also available in standard "off the shelf" configurations; the 3301 A was manufactured using Schottky barrier diode clamped transistors which allowed higher switching speeds.
- Fast access time: 45 nsec
- Power dissipation 0.5 mW/bit
- DTL and TTL compatible
- Input loading .25 mA max.
- Outputs sink 15 mA
- Aimple memory expansion - 2 chip select input leads
- Fully decoded on-chip address decode and buffer

3601

1024-bit electrically programmable Schottky Bipolar Read Only Memory; the 3601 is suited for uses where fast turnaround and pattern experimentation are important such as in prototypes or in small production volume systems; the 3601 is pin compatible with the Intel mask ROMs 3301 or 3301A; the 3601 is manufactured using Schottky barrier diode clamped transistors which allows faster switching speeds than those devices made with conventional gold diffusion process.
- Fast programming - 2 ms / bit typically
- Fast access time - 70 nsec max.
- Power dissipation 0.5 mW / bit typically
- DTL and TTL compatible
- OR-Tie Capability - open collector outputs
- Simple memory expansion - 2 chip select input leads

U 61xxx

The U 61000 was the very first and very last 1 Mbit DRAM of German Democratic Republic. It has been introduced in 1989 (Leipziger Frühjahrsmesse). Since GDR collapsed in November 1989 not many of the U 61000 have been produced.

see article published in November 1988