8080

The 8080 was designed as an enhanced version of the 8008 (increased number of signal inputs and outputs, increasing of efficiency about ten times, only six peripheral chips needed, extended instruction set, N-Channel MOS technology).

Four persons were responsible for the development of the 8080:
- Ted Hoff, Stan Mazor: responsible for the instruction set
- Federico Faggin, Masatoshi Shima: circuit layout

The 8080 was the technical initialization for the world-wide microprocessor market. Within one year after the introduction the 8080 was implemented into hundreds of different components. Due to the low production costs of a microprocessor several clone manufacturers sprouted up as well as competitors with other chip designs (Mostek, Synertek).

Fabricated on a single LSI chip using N-channel silicon gate MOS technology.
Unlike the 8008 the 8080 was not manufactured in MOS but in NMOS technology. This allows a faster manufacture procedere.
To preserve the customers investment in software the 8080 was software compatible to the 8008. Additional to this advantage large system-type features were included on-chip such as DMA, 16-bit addressing and external stack memory. Two further features of the 8080 CPU are the exclusion of clock logic and bus interface logic from the CPU chip.
The 8080 requires three power-supply voltages: +5 V, -5 V, +12 V and two clock inputs. Because of the potential of 17 V and the increased number of pins the speed of 8080 was much higher than the speed of the 8008. Improvements in the 17-volt MOS manufacturing process have resulted in benefits other than higher speed. The size of the silicon die on which the 8080 is etched had been reduced from one manufacturer to another ( 230 by 210 mils, or 48,300 square mils to 131 by 169 mils, or 22,139 square mils). This led to a reduction in cost since more 8080s could be produced from each silicon wafer.
Can address up to 65,536 words of memory and has 78 types of instructions. The last ten operating codes were not used.

Improvements of 8080A vs. 8080:
- Some improvements in timings to prior specs to improve the yield. Power delivery
  on-die was made more robust.
- Output buffer size increased to improve IOL to 1.9 mA at 0.45 volts to allow driving a
  standard TTL load.
- Clock timing between PH1 and PH2 (tD3) improved to make clock generation not a
  problem.
- INT synchronized to the falling edge of PH2 during the last cycle of the instruction and
  during HALT. Also, the PC register is not incremented during the interrupt instruction so
  that any branch instruction can be executed. The MEMR is held inactive during M1 of
  an interrupt instruction. MEMR can still happen in M2 and M3. The 8228 interface chip
  blocked MEMR in those cycles and provided the proper INTA signals.
- HOLD was resampled internally during not PH2 to make it fully asynchronous. The
  signal is sampled on PH2 rising during T2.
- Internal logic changed to allow RESET to be an effective interrupt to address 0 (zero).

Improvements of 8080B vs. 8080A:
- functional and characterized in the second Quarter of 1978. The design was done
  through Intels Israel Design Center.
- Completely compatible with the 8080A (functional and pin compatible).
- Newer process with slightly smaller feature size (still enhancement-mode only
  transistors.)
- Above results in smaller die size.
- About 30% lower power.
- Timings improved to allow 3 MHz clock speed and significant yield to 4 MHz.
- IOL improved again to 3.2 mA to drive more loads.
- VIH improved to 2.4 V to be more compatible to standard logic types of the period.
- Allows 10% tolerance supplies vs. 5% supplies.

8080A: 2.0 MHz
8080A-1: 3.125 MHz
8080A-2: 2.67 MHz

AMD, Mitsubishi, National Semiconductor, NEC, OKI, NTE, Siemens, Signetics, Tesla, Texas Instruments, USSR clones
Siemens manufactured the 8080A familiy in Europe with the active support of Intel; although AMD developed the first of their 8080A products without authorization it came to a second source agreement with Intel; all other 8080A manufacturers were unauthorized
Of the 8080A devices which have been available on the market, the NEC 8080D was the only one that differed significantly from the Intel 8080A. NEC´s 8080D was advertised as an upward enhancement. Some of the NEC 8080D enhancements did not execute programs correctly which have been written for Intel 8080A.
Besides the MP 8080 AI Signetics also offered an 8080 emulator as a kit. It was designed as a single board computer compatible with Intel's SBC 80 series. Intended as an example of the application of the 3002 bit-slice microprocessor it used 61 chips, including eight 3002's and one 3001, to emulate a 7-chip 8080 CPU system.

                    Miscellaneous

development kit

Technology

Kit consists of 1xC8080A, 4xC1702A, 5x8212, 8x2102A, 1x8205, 1x8224

PROM Programmer for UV erasable, electrically reprogrammable ROMs (EPROMs); fully assembled microcomputer design aid; simplifies the programming of SBC 80 and system 80 microcomputers, as well as 8080 processors, 8708 / 2708 / 2704 / 8755 EPROMs and 8255 / 8251 programmable I/O devices; many 8080 operations can be specified with only two key strokes; once entered, programs can be exercised one instruction (single step) or many instructions at a time; any of the 8080 registers can be watched while single-stepping; programs are readily saved and instantly reloaded via UV erasable, electrically reprogrammable ROMs (EPROMs); PROMPT 80/85 can program the 8708 EPROMs in small blocks, so routines can be debugged and saved incrementally; several programs are pre-recorded as examples on PROMPT's spare 8708 EPROMs; includes an integral keyboard and 16-digit display, so no tele-typewriter or CRT terminal is required.

Technology

Microcomputer design aid including standard 8080A CPU on SBC 80/10 Single Board Computer, 1Kbyte RAM, 3Kbyte ROM, 24 programmable parallel I/O (TTL) lines, incl. two 8-bit ports; fully implemented switches, displays, programmable serial I/O interfaces, 110 or 230 V AC required;
The heart of PROMPT 80 is a SBC 80/10 Single Board Computer, a complete computer on a single printed circuit board; the SBC 80/10 includes an 8080A, 1Kbytes of static RAM and sockets for 4 Kbytes of EPROM; signals to the SBC 80/10 include 48 programmable, parallel I/O lines with sockets for interchangeable line drivers and terminators, a programmable serial channel, a multi-source single level interrupt network, and bus drivers for memory and I/O expansion; ROM may be added in 1 Kbyte increments using Intel 8708 EPROMs or 8308 ROMs;
Central processor for PROMPT's SBC 80/10 is a 8-bit n-channel MOS 8080A CPU.

Fully packaged rack-mountable microcomputer system including the SBC 80/20 with three slots for standard or custom expansion boards; 3.5-inch high, 19-inch wide rack-mountable chassis; heavy duty power supply 

Technology

The heart of SBC 655 is a SBC 80/20 Single Board Computer including an 8080A; 2Kbytes of static RAM and sockets for up to 8 Kbytes of ROM / EPROM; signals to the SBC 80/20 include 48 programmable, parallel I/O lines; programmable synchronous / asynchronous communications interface; two programmable 16-bit BCD or binary interval timers / event counters; clock rate 2.15 MHz
Central processor for SBC 80/20 is a 8-bit n-channel MOS 8080A CPU.

Comment

NEC D8080A socked on board, enhanced version of D8080AF; fabricated in NMOS technology

Single board computer

Technology

socket on board:    8080AF: CPU (pin compatible to D8080A, NMOS technology)
                            D458D:  EPROM 1024x8
soldered on board: B8228C: System Controller
                            D8253C: Programmable timer
                            D8255C: Peripheral interface
                            D8259C: Programmable interrupt controller

Comment

Block made out of acrylic glass with inserted Siemens SAB 8080 microprocessor for education purposes. Block was manufactured by "Bereich Bauelemente" (= devision electronic components)