65816

The W65C816S is a low power cost sensitive 16-bit microprocessor. The variable length instruction set and manually optimized core size makes the W65C816S a choice for low power System-on-Chip (SoC) designs. The Verilog RTL model is available for ASIC design flows. Western Design Center (WDC) provides packaged chips for evaluation or volume production. The WDC W65C816 is a fully static CMOS 16-bit microprocessor featuring software compatibility with the 8-bit NMOS and CMOS 6500-series predecessors. The W65C816 extends addressing to a full 16 megabytes. A software switch determines whether the processor is in the 8-bit "emulation" mode, or in the native mode, thus allowing existing systems to use the expanded features.

- Advanced fully static CMOS design for low power consumption and increased
  noise immunity

- Wide operating voltage range, 1.8+/- 5%, 2.5+/- 5%, 3.0+/- 5%, 3.3+/- 10%,
  5.0+/- 5% specified for use with advanced low voltage peripheralsEmulation mode
  allows complete  hardware and software compatibility with 6502 designs

- 24-bit address bus provides access to 16 MBytes of memory space

- Full 16-bit ALU, Accumulator, Stack Pointer and Index RegistersValid

- Data Address (VDA) and Valid Program Address (VPA) output for dual cache and
  cycle steal DMA  implementation

- Vector Pull (VPB) output indicates when interrupt vectors are being addressed

- Abort (ABORTB) input and associated vector supports processor repairs of bus
  error conditions

- Low power consumption (300uA@1MHz)

- Separate program and data bank registers allow program segmentation or full 16
  MByte linear  addressing

- New Direct Register and stack relative addressing provides capability for
  re-entrant, re-cursive and re-locatable programming

- 24 addressing modes - 13 original 6502 modes with 92 instructions using 256
  OpCodes

- Wait-for-Interrupt (WAI) and Stop-the-Clock  (STP) instructions further reduce
  power consumption, decrease interrupt latency and allows synchronization with
  external events

- Co-Processor (COP) instruction with associated vector supports co-processor
  configurations, i.e., floating point processors

- Block move ability